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mos integrated circuit the information in this document is subject to change without notice. ? 1998 m m m m PD23C128040L 128m-bit mask-programmable rom 16m-word by 8-bit (byte mode) / 8m-word by 16-bit (word mode) page access mode document no. m13643ej1v0ds00 (1st edition) date published august 1998 ns cp (k) printed in japan preliminary data sheet the mark ? ? ? ? shows major revised points. description the m PD23C128040L is a 134,217,728 bits mask-programmable rom. the word organization is selectable (byte mode: 16,777,216 words by 8 bits, word mode: 8,388,608 words by 16 bits). the active levels of oe (output enable input) can be selected with mask-option. the m PD23C128040L is packed in 48-pin plastic tsop(i). features word organization 16,777,216 words by 8 bits (byte mode) 8,388,608 words by 16 bits (word mode) page access mode byte mode : 8 byte random page access word mode : 4 word random page access operating supply voltage : 2.7 to 3.6 v operating supply voltage v cc access time / page access time ns (max.) power supply current (active mode) ma(max.) standby current (cmos level input) m a(max.) 3.3 v 0.3 v 100 / 30 60 30 3.0 v 0.3 v 120 / 40 55 30 ordering information part number package m PD23C128040Lgy- xxx-mjh 48-pin plastic tsop(i)(12 x 18 mm)(normal bent) m PD23C128040Lgy- xxx-mkh 48-pin plastic tsop(i)(12 x 18 mm)(reverse bent) (xxx: rom c ode suffix no.)
2 m m m m PD23C128040L preliminary data sheet pin configuration (marking side) /xxx indicates active low signal. 48-pin plastic tsop(i) (12 x 18 mm) (normal bent) [ m m m m PD23C128040Lgy-xxx-mjh] word, /byte a16 a15 a14 a13 a12 a11 a10 a9 a8 a19 a21 a20 a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 /ce gnd gnd o15, a-1 o7 o14 o6 o13 o5 o12 o4 v cc v cc a22 o11 o3 o10 o2 o9 o1 o8 o0 /oe, oe, dc gnd gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a0 - a22 : address inputs o0 - o7, o8 - o14 : data outputs o15, aC1 : data 15 output(word mode), lsb address input(byte mode) word, /byte : mode select /ce : chip enable /oe, oe : output enable v cc : supply voltage gnd : ground dc : dont care
3 m m m m PD23C128040L preliminary data sheet 48-pin plastic tsop(i) (12 x 18 mm) (reverse bent) [ m m m m PD23C128040Lgy-xxx-mkh] word, /byte a16 a15 a14 a13 a12 a11 a10 a9 a8 a19 a21 a20 a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 /ce gnd gnd o15, a-1 o7 o14 o6 o13 o5 o12 o4 v cc v cc a22 o11 o3 o10 o2 o9 o1 o8 o0 /oe, oe, dc gnd gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a0 - a22 : address inputs o0 - o7, o8 - o14 : data outputs o15, aC1 : data 15 output(word mode), lsb address input(byte mode) word, /byte : mode select /ce : chip enable /oe, oe : output enable v cc : supply voltage gnd : ground dc : dont care
4 m m m m PD23C128040L preliminary data sheet input/output pin functions pin name input/output function word, /byte input the pin for switching byte mode and word mode. high level : word mode (8m-word by 16-bit) low level : byte mode (16m-word by 8-bit) a0 to a22 (address inputs) address bus. a0 to a22 are used differently in the word mode and the byte mode. word mode (8m-word by 16-bit) a0 to a22 are used as 23 bits address signals. byte mode (16m-word by 8-bit) a0 to a22 are used as the upper 23 bits of total 24 bits of address signal. (the least significant bit (a - 1) is combined to o15.) o0 to o7, o8 to o14 (data output) output output data bus. o0 to o7, o8 to o14 are used differently in the word mode and the byte mode. word mode (8m-word by 16-bit) the lower 15 bits of 16 bits data outputs to o0 to o14. (the most significant bit (o15) combined to a - 1.) byte mode (16m-word by 8-bit) 8 bits data outputs to o0 to o7 and also o8 to o14 are high impedance. o15, a - 1 (data output 15) , (lsb address input) input, output o15, a - 1 are used differently in the word mode and the byte mode. word mode (8m-word by 16-bit) the most significant output data bus (o15). byte mode (16m-word by 8-bit) the least significant address bus (a - 1). /ce (chip enable) input chip activating signal. when the oe is active, output states are following. high level : high impedance low level : data out /oe, oe, dc (output enable) input output enable signal. the active level of oe is mask option. the active level of oe can be selected from high active, low active and dont care at order. v cc - supply voltage gnd - ground
5 m m m m PD23C128040L preliminary data sheet block diagram a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 o15, aC1 word, /byte /oe, oe, dc /ce output buffer y-selector memory cell matrix 8,388,608 by 16 bits/16,777,216 by 8 bits address input buffer x-decoder logic/input input buffer y-decoder a19 o14 o13 o12 o11 o10 o9 o8 o0 o1 o2 o3 o4 o5 o6 o7 a20 a21 a22
6 m m m m PD23C128040L preliminary data sheet mask option the active levels of output enable pin (/oe, oe, dc) are mask programmable and optional, and can be selected from among " 0 " " 1 " " x " shown in the table below. option /oe, oe, dc oe active level 0/oe l 1oe h x dc dont care operation modes for each option are shown in the tables below. operation mode (option: 0) /ce /oe mode output state l data out l h active high impedance h h or l standby high impedance operation mode (option: 1) /ce oe mode output state l high impedance l h active data out h h or l standby high impedance operation mode (option: x) /ce dc mode output state l h or l active data out h h or l standby high impedance remark l: low level input h: high level input
7 m m m m PD23C128040L preliminary data sheet electrical specifications absolute maximum ratings parameter symbol condition rating unit supply voltage v cc C0.3 to +4.6 v input voltage v i C0.3 to v cc +0.3 v output voltage v o C0.3 to v cc +0.3 v operating ambient temperature t a C10 to +70 c storage temperature t stg C65 to +150 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. capacitance (t a = 25 c) parameter symbol test condition min. typ. max. unit input capacitance c i 10 pf output capacitance c o f = 1 mhz 12 pf dc characteristics (t a = C10 to +70 c, v cc = 2.7 to 3.6 v) parameter symbol test conditions min. typ. max. unit high level input voltage v ih 2.0 v cc + 0.3 v low level input voltage v il v cc = 3.0 v 0.3 v C0.3 +0.5 v v cc = 3.3 v 0.3 v C0.3 +0.8 high level output voltage v oh i oh = C100 m a2.4v low level output voltage v ol i ol = 2.1 ma 0.4 v input leakage current i li v i = 0 v to v cc C10 +10 m a output leakage current i lo v o = 0 v to v cc , chip deselected C10 +10 m a power supply current i cc1 /ce = v il (active mode), v cc = 3.0 v 0.3 v 55 ma i o = 0 ma v cc = 3.3 v 0.3 v 60 standby current i cc3 /ce = v cc C 0 . 2 v (standby mode) 30 m a
8 m m m m PD23C128040L preliminary data sheet ac characteristics (t a = C10 to +70 c, v cc = 2.7 to 3.6 v) parameter symbol test condition v cc = 3.0 v 0.3 v v cc = 3.3 v 0.3 v unit min. typ. max. min. typ. max. address access time t acc 120 100 ns page access time t pac 40 30 ns chip enable access time t ce 120 100 ns output enable access time t oe 40 30 ns output hold time t oh 00ns output disable time t df 0 30 0 25 ns word, /byte access time t wb 120 100 ns remark t df is the time from inactivation of /ce or /oe, oe to high-impedance state output. ac test conditions input waveform (rise / fall time 5 ns) test points 1.4 v 1.4 v output waveform test points 1.4 v 1.4 v output load 1ttl + 100 pf
9 m m m m PD23C128040L preliminary data sheet read cycle timing chart 1 a0 to a22, aC1 note 1 (input) o0 to o7, note 3 o8 to o15 (output) /ce (input) /oe, oe (input) t acc t ce t oe t df note 2 t oh data out high impedance notes 1. during word mode, aC1 is o15. 2. t df is specified when one of /ce, /oe, oe is inactivated. 3. during byte mode, o8 to o14 are high impedance and o15 is aC1.
10 m m m m PD23C128040L preliminary data sheet read cycle timing chart 2 (page access mode) a0 to a22 (input) /ce (input) /oe, oe (input) t acc data out t ce t oe t pac note 4 t pac note 4 o0 to o7, note 3 o8 to o15 aC1, note 1 a0, a1 (input) (output) data out data out high impedance high impedance t oh t oh t oh t df note 2 notes 1. during word mode, aC1 is o15. 2. t df is specified when one of /ce, /oe, oe is inactivated. 3. during byte mode, o8 to o14 are high impedance and o15 is aC1. 4. the definition of page access time is as follows. page access time upper address (a2 to a22) inputs condition /ce input condition /oe, oe input condition t pac before t acc C t pac before t ce C t pac before stabilizing of page address (aC1, a0, a1)
11 m m m m PD23C128040L preliminary data sheet word, /byte switch timing chart data out aC1 (input) word, /byte (input) data out data out high impedance o0 to o7 (output) o8 to o15 (output) t oh t acc t oh t wb data out data out t df high impedance high impedance remark /oe, oe and /ce : active.
12 m m m m PD23C128040L preliminary data sheet package drawings notes 48 pin plastic tsop ( i ) (12 18) item millimeters inches a b c e i 12.00.1 0.5 (t.p.) 0.10.05 0.45 max. k 1.2 max. 16.40.1 0.1450.05 f 0.10 m 0.472 0.018 max. 0.0040.002 0.646 0.006 0.048 max. 0.004 0.020 (t.p.) d 0.220.05 0.009 2. each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. 3. "a" excludes mold flash. (includes mold flash : 12.4 mm max. <0.489 inch max.>) c r d k m m l +0.002 C0.003 1.00.05 g 0.039 +0.003 C0.002 +0.004 C0.005 l 0.5 0.020 0.10 n 0.004 p 18.00.2 0.709 +0.008 C0.009 q 0.25 r 0.010 s48gy-50-mjh1 s 0.600.15 0.024 +0.006 C0.007 +0.002 C0.003 j 0.80.2 0.031 +0.009 C0.008 +0.005 C0.004 1 24 48 25 s q s n i p b e g f a j detail of lead end s 1. controlling dimension millimeter. +5 ? C3 ? 3 ? +5 ? C3 ? 3 ?
13 m m m m PD23C128040L preliminary data sheet notes 48 pin plastic tsop ( i ) (12 18) item millimeters inches a b c e i 12.00.1 0.5 (t.p.) 0.10.05 0.45 max. k 1.2 max. 16.40.1 f 0.10 m 0.472 0.018 max. 0.0040.002 0.646 0.048 max. 0.004 0.020 (t.p.) d 0.220.05 0.009 2. each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. 3. "a" excludes mold flash. (includes mold flash : 12.4 mm max. <0.489 inch max.>) c b r k d m m +0.002 C0.003 1.00.05 g 0.039 +0.003 C0.002 +0.004 C0.005 l 0.5 0.020 0.10 n 0.004 p 18.00.2 0.709 +0.008 C0.009 q 0.25 r 0.010 s48gy-50-mkh1 s 0.600.15 0.024 +0.006 C0.007 j 0.80.2 0.031 +0.009 C0.008 0.1450.05 0.006 +0.002 C0.003 +0.005 C0.004 1 24 48 25 s n a i p j g f l s q e detail of lead end s 1. controlling dimension millimeter. +5 ? C3 ? 3 ? +5 ? C3 ? 3 ?
14 m m m m PD23C128040L preliminary data sheet recommended soldering conditions please consult with our sales offices for soldering conditions of the m PD23C128040L. types of surface mount device m PD23C128040Lgy-mjh : 48-pin plastic tsop(i)(12 x 18 mm)(normal bent) m PD23C128040Lgy-mkh : 48-pin plastic tsop(i)(12 x 18 mm)(reverse bent)
15 m m m m PD23C128040L preliminary data sheet notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
m m m m PD23C128040L [memo] no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec?s data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative.

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